1. Field of the Invention
This invention relates generally to circuits and processes for converting digital codes to analog signals, and, more particularly, to parallel digital-to-analog converter topologies.
2. Description of Related Art
Improvements to data conversion products, such as digital-to-analog converters (DACs), generally involve steps for increasing precision and/or speed. As is known, one way of increasing precision without sacrificing speed is to operate multiple DACs in parallel.
FIG. 1 shows a topology 100 of parallel DACs according to the prior art. A plurality of DACs 110, 112, 114, 116 is connected in parallel. Each DAC receives the same input code (Code In) and generates an output signal in response to the input code. A combining circuit 118 combines the output signals from the DACs to produce an overall output signal, VOUT.
As is known, each of the DACs in the topology 100 is susceptible to noise. The level of this noise limits the precision of the individual DACs. Because noise is generally random, averaging the outputs of the DACs reduces its overall effect. In the parallel configuration 100, adding the outputs of the individual DACs averages out the noise without adversely affecting speed. For N DACs connected in parallel, noise is known to be reduced by approximately one over the square root of N.
Although the topology of FIG. 1 effectively reduces noise, we have recognized that it does not generally reduce linearity errors. As is known, linearity errors are erroneous deviations in a DAC's output signal as input code is varied. Ideally, the output of a DAC versus input code should be a perfect stair-step function that accurately mirrors the discrete steps of the digital input code. Imperfections within the DAC, however, may cause certain “steps” to be too long or too short, giving rise to an error known as differential non-linearity (DNL). In addition, the overall path of the stair-step function can deviate from the ideal path, giving rise to an error known as integral non-linearity (INL). We have recognized that, far from being random, these DNL and INL errors tend to be repeatable among different DACs of the same type. Because they are repeatable, averaging does not generally reduce their effects.
What is needed, therefore, is a DAC topology that reduces linearity errors as well as noise.